liberty , Scripting, Tcl, python, Pcie, DDR, IO standards, bump map pattern definition, pad ring planning, RTL, Isp, EDA Tools, IO cell placement, PHY-level IO interfaces, Orbit IO, CXL, IO library cells, flow automation, lef, SERDES

static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, LINT, SystemVerilog RTL design, formal verification, Dft, cdc, Logic Synthesis