Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Perl, Debugging, Bash, Python, Tcl, SoC Verification, verification environments, standard bus protocols, Uvm, systemverilog

UFS (Universal Flash Storage), C, C++, Makefile, Perl, Verilog, Ethernet, System Verilog, Verification tools such as VCS, System Verilog verification language, Uvm, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol

Scala, Python, System Verilog, Chisel, Uvm