Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL

Load Balancing, Prometheus, OpenStack, Dns, Grafana, Devops, Jenkins, Gcp, Linux, Terraform, Ansible, Azure, Kubernetes, Python, AWS, Go, Sumo Logic, Elastic Stack, AI-assisted development tools, Site Reliability Engineering, Infrastructure Engineering, Networking fundamentals, Platform Engineering

Java, Cassandra, PostgreSQL, Spring Boot, Sql, Microservices, Rest Api, Nosql, React, Figma, Gcp, Javascript, MySQL, MongoDB, Azure, Python, AWS, Opik, Traces, Lang Graph, Claude, Lang smith, Multi-Agent Systems

Java, Jenkins, Gcp, Terraform, Kubernetes, Python, AWS, Spinnaker, Go, ArgoCD, IaC