Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging

System Verilog, Post-silicon validation, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures

Vcs, System Verilog, primetime, Tessent, JTAG protocols, Logic Equivalency checking, ATPG, EDA Tools, TestMax, TetraMax, Scan and BIST architectures

data streaming , Github, Apis, Data Modeling, PostgreSQL, Performance Tuning, Pyspark, Pl Sql, Autosys, Db Design, Sql, Unix Shell Scripting, Agile Software Development, Apache Kafka, Oracle, Python, AWS, Airflow, NoSQL databases, Data Bricks

Java, Scala, Node.JS, Python, Advanced prompt engineering skills, Large-scale system architecture, Agile Scrum methodologies, Go, AI-first approach to engineering, Full-stack software development

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, P1687, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATE patterns, Tessent, JTAG protocols, ATPG, EDA Tools, TestMax

Prince2, Java, Python, Lean Six Sigma Green Belt or Black Belt, Project Management, Prosci Change Management Certification, Agile Scrum Certification, PMP Project Management Professional