Tcl, C, Debugging, Shell, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, assertions, formal verification methodologies

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

Garbage Collection, Nvme, Test Strategies, Pcie, Python, Automated reporting systems, Wear levelling, SSD NAND architecture, Qualification methodologies, Test infrastructure, Error Handling and Recovery Flows, Reliability and Endurance Validation, Quality dashboards, Bad block management, Embedded Firmware development, Validation plans, Error injections, NAND Management, Cloud SSD specifications

Pcie, Verification IPs, Regression systems, Simulation environments, VIP abstraction layers, Industry-standard simulators, CXL, Transaction-based verification methodologies, Revision control systems, Uvm, Assertions

Unix Shell, Tcl, Python, Perl, LVS, IC Validator, Cadence Virtuoso, DRC, Calibre, PERC

C, Python, LabVIEW, SoC System-on-Chip, precision measurement techniques, voltage regulators, reference circuits, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers

System Verilog, UVM methodology

UVM methodology, System Verilog coding, UVM-based verification frameworks