IC design, Packaging requirements, Design IP process technology, Power management design, Verification

Nvme, SAS, Silicon Validation, Pcie, Verilog, physical implementation, Synthesis, functional safety, Architecture Design, verification methodologies, Reliability, advanced verification techniques, Uvm, tape-out, silicon security, systemverilog, Rtl Design, Dft, Timing Closure, performance optimization, CXL, power management, Design Methodologies

Eda, Machine Learning, Artificial Intelligence, automation, physical implementation, semiconductor design automation, agentic AI, extraction and simulation workflows, generative AI, design migration and design reuse, analog and custom IC design, LVS, OpenAccess-based design environments, Physical Verification, semiconductor design, circuit simulation SPICE, DRC, Parasitic Extraction, analog verification flows, standard cell design and optimization, Cadence Virtuoso

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis