power optimization , Perl Scripting, CTS, Block level PnR convergence, Cadence Innovus, LVS, Physical Implementation, Timing convergence, Physical Verification, Timing Closure, DRC, PDN, STA concepts, Floor-planning, PD implementation of PPA critical Cores, Place And Route, Synopsys ICC2, formal verification, Clocking architecture

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, ICV, Synopsys

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

static timing analysis, Floor Planning, Synthesis, Makefile scripting, physical design CAD flow, physical design verification, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus