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What Will You Be Doing

Participate in ground breaking Processor design and debug in deep submicron technologies.
Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.
Responsible for generating ATPG patterns for Silicon speed path debug.
RTL and gate level verification for ATPG, non-ATPG patterns.
Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.
RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon
Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run
Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.

What We Need To See

BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.
Good understanding of Design-for-test(DFT) and logic design is required.
Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.
Basics of circuits and RAM functionality/architecture will be helpful.
Experience in VLSI simulation tools like VCS etc
Experience with pattern generation using tools such as tessent.
Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.
Prior experience in STA and basic understanding of circuit concepts will help in the role.
Post-Silicon data gathering experience is a plus.

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.

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Senior Circuit Silicon Correlation DFT Engineer