Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus

C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools

Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS

power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS

Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation

Physical Design, Synthesis, RTL2GDS, primetime, floorplanning, EDA Tools, Synopsys Fusion Compiler, Cadence Innovus, Tempus

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation