spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

Verilog, debug tools like Debussy GDB, bring-up lab debug, ASIC design flow, floor-planning, Timing Analysis, VCS or equivalent simulation tools, Eco, Rtl Design

multi-domain clock synchronization, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, high performance memory subsystems, ASIC debugging