Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

C, Perl, Python, Fpga, Emulation platforms, Uvm, systemverilog, AMBA bus protocols, Transaction level modeling, Automation scripts, RTL

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, SoC IP architecture and verification methodologies, UVM methodology, systemverilog, Functional Verification, Coverage-driven verification

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

code coverage , Nvme, Pcie, Ethernet, System Verilog, DDR, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB, BFMs, Scoreboards, Checkers, Monitors, Functional coverage, Assertions

Perl, Vcs, Python, Tcl, Uvm, Verdi, Questa, systemverilog

bandwidth management , Universal Verification Methodology (UVM), Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, revision control systems, packet processing, AI ML Accelerators, constrained-random verification environments, Verification