Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

Python, Tcl, Logical design, Digital design flows, systemverilog

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA

Perl, Verilog, Python, Uvm, SVA, systemverilog

Java, C, multithreading, Python, AI tools, LSF concepts, debugging skills, EDA flow Automation, multiprocessing

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, ICV, Synopsys