Verilog, MATLAB, Xilinx FPGA tools, VHDL, digital hardware circuitry, FPGA development, Simulink, measurement and debugging tools

Verilog, FPGA Design, Intel Altera Quartus, VHDL, FPGA debugging, Libero SoC, Oscilloscopes, AMD Vivado, logic analyzers

VHDL programming, Xilinx, FPGA development, hardware debugging, Intel Altera, Timing Closure, RFSoC, Vivado, Modelsim, LabVIEW FPGA, Rtl Design, Simulation

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

rtl development , nand flash , Tcl, Verilog, FPGA Design, Python, Bash, Pcie, IP Integrator, Vivado Design Suite, VHDL, ChipScope ILA, Embedded Systems, Xilinx FPGAs

Tcl, Verilog, Python, Perl, VHDL, systemverilog, Vivado, quartus