Ovm, DDR, Pcie, Python, Tso, Perl, Ethernet, Arm, Tcl, systemverilog, RISC-V, LRO, Uvm, AI Compute, SV Assertions, HBM, Formal Emulation, Die-to-Die Interconnects, RDMA, High-Speed IO Interconnects, RoCE, NIC, 400G MAC, TimeSync protocols, revision control systems

UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, Synopsys VIPs, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol, waveform analyzer

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

DDR, Pcie, Ethernet, GIC, CMN, Low-Speed Peripherals, SMMU, RISC-V Cores, eMMC, CoreSight, SoC-level Design Verification, SV, Low-Power Verification, ARM v8 v7 Cores, Uvm, UPF

Spi, Uart, I2c, Ethernet, Can, DV firmware verification, GLS, Uvm, Specman, systemverilog, AMS CDC digital verification, post-silicon verification, AHB, C-based SoC design verification, UPF based verification, CSI, CPF, cybersecurity processes, AI ML based DV, formal verification, APB, Axi, functional safety, PAGLS

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles