Verilog, MATLAB, Xilinx FPGA tools, VHDL, digital hardware circuitry, FPGA development, Simulink, measurement and debugging tools

Verilog, FPGA Design, Intel Altera Quartus, VHDL, FPGA debugging, Libero SoC, Oscilloscopes, AMD Vivado, logic analyzers

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4

Spi, Pcie, Perl, Verilog, Ethernet, I2c, Python, Tcl, hardware-software integration, Otn, IP integration, systemverilog, transport system design, quartus, Vivado, MDIO, FPGA design methodologies

microblaze , synplify , nios ii , Vcs, Shell, Verilog, Tcl, Ethernet, Python, Pcie, DDR, quartus, Questa, systemverilog, Lattice FPGAs, Vivado, Modelsim, VHDL, Xilinx, Intel Altera, ARM SoCs, Axi

Tcl Scripting, Vivado Quartus or Libero Tools, RTL Design using Verilog VHDL, Hardware Debugging and Board Bring-up, FPGA Design Flow Synthesis Implementation P R Timing Closure, High-Speed Protocols PCIe Ethernet DDR Transceivers, FPGA Design and Validation, CDC Clock Domain Crossing Analysis, Simulation using Questasim, FPGA Integration Experience, Experience using Oscilloscopes and Logic Analyzers, Static Timing Analysis STA

FPGA Design, Static Timing Analysis, Synthesis, Timing Closure, systemverilog, Code coverage analysis, RTL design using Verilog

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing